Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

PDF) Improved Air Spacer for Highly Scaled CMOS Technology

DTCO flow for air spacer generation and its impact on power and

DTCO flow for air spacer generation and its impact on power and performance at N7 - ScienceDirect

Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era - ScienceDirect

Process integration and future outlook of 2D transistors

PDF) Improved Air Spacer for Highly Scaled CMOS Technology

Directed self-assembly for ever-smaller printed circuits

PDF) FinFET scaling to 10 nm gate length