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Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size and lower cost of electronic consumer products. Wafer bumping is unavoidable process in flip chip packaging, thus, picking the correct bumping technology that is capable of bumping silicon wafer at high yield and a high reliability with lower cost is challenging. This paper discusses the available wafer bumping technologies for flip chip packaging. The discussion will be focused on process assembly, solder ball compatibility, design structure and lastly cost which translated to overall product costs.
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